1. Technical Field
The present invention relates generally to circuit production methodologies using redundant elements for repair, and more particularly to a method and computer program for optimally selecting elements for repair using redundancies by considering aging effects.
2. Description of the Related Art
Improvement in performance and yield in memory arrays is presently provided by provision of redundant circuit elements. Depending on memory organization, extra row or column circuits are included in the memory array circuit, and depending on production test results, if an array element fault is detected, the column or row can be replaced, or in some implementations, individual cells may be replaced. The replacement process typically uses metal layer fuses or masks, or replacement logic responsive to stored values. The masks, fuses or values can be altered during the production process to effect the replacement of the column/row or individual cells. The fault may be that a cell or row/column is un-writable or unreadable, or the fault may be a failure to meet a specified performance criteria such as read timing margins or minimum write time/write stability under all operating conditions.
Due to the number of redundant elements typically provided in a repairable array, a selection is typically made to provide the best possible performance among the possible combinations of repairs. The provision of redundancy and the selection flexibility can provide yields at the level of 5σ and beyond for the initial production yield, provided sufficient redundant elements are supplied. Optimized selection of the repair elements can be performed to provide present-time normalization of the device with respect to “process corners” for each design or at least each production run, so that at initial production, the device is positioned as close as possible to the theoretical nominal device, within the limitations of the number of redundant elements not already used to repair hard faults or elements that fall outside of minimum/maximum specified performance parameters. However, such repair selection results in an optimization of yield that takes into account only the performance at the beginning of life of the device.
Electronic devices in general, and very small feature devices such as memory arrays specifically, have limited lifetime due to various aging effects. The mean time between failure (MBTF) of a memory array is a consideration of long-term performance, and therefore the robustness of the design typically must exceed the level of initial performance by some factor, in order to ensure that the minimum level of performance is maintained throughout the expected lifetime of the device. Of particular concern are effects such as negative bias temperature instability (NBTI), which makes P-MOS devices weaker under stress applied over time due to diffusion of materials in the gate oxide. Also more recently of concern is positive bias temperature instability (PETI), which has an opposite effect on operating point. Since aging effects are a time/stress and time/temperature relationship, long-term aging effects may in fact be short-term, depending on stress levels applied. Therefore, in general, memory array designs are made sufficiently robust to ensure proper operation over all environmental ranges (e.g., temperature and supply voltage) for the design lifetime of the device.
Aging effects are typically compensated-for by testing a larger number of process corners that are extended in range to accommodate the expected margin needed throughout the life of the product. However, the additional test time and resources required to perform such testing increases manufacturing cost and/or reduces production throughput and can lead to a less-than-optimal selection of repair elements for optimizing device yield with respect to the entire device lifetime.
It would therefore be desirable to provide a method and computer program for efficiently optimizing selection of repair elements while taking aging considerations into account, so that the optimum selection of repair elements is not toward an initial nominal device for the design or production run with or without extended performance margins, but rather toward a device performance that will yield the optimum long-term performance and lifetime.